When producing integrated circuits, a number of process layers are formed on a substrate, each process layer incorporating a layout pattern. The layout patterns within the various layers establish component features and interconnections such that once the final process layer is formed, an integrated circuit containing all of the required circuit components interconnected in the manner required to perform the functions of the integrated circuit is produced.
For a new integrated circuit (IC), a layout of that integrated circuit will be produced in the form of a data file identifying the required layout patterns for each of the process layers. To assist in the generation of such a layout, it is known to use cell libraries providing a plurality of different cells, each cell defining a layout for a particular component. Various types of cells are used in modern systems for generating integrated circuit layouts, for example standard cells, datapath cells, custom cells, cells representing portions of a memory device, etc. For purposes of the following discussions, the standard cell example will be referred to herein.
A standard cell library will provide a plurality of standard cells, each standard cell defining a layout for a particular circuit component. The circuit components for which standard cells are developed are typically the basic building block components (e.g., AND gates, NAND gates, OR gates, NOR gates, inverters, flops, etc.) used to construct more complex circuits within the integrated circuit.
Once a standard cell library has been produced for a particular process technology, the design of integrated circuits for that process technology can be simplified. For example, it is known to provide automated tools which use a functional design of a planned integrated circuit (for example in the form of a gate level net list or a Register Transfer Language (RTL) higher level representation of the design) and a standard cell library in order to generate the layout of the planned integrated circuit.
Typically, the standard cells are arranged in rows by the automated tool. Considering the rows run horizontally, the left and right boundaries of each standard cell may be placed next to any other given standard cell. Thus the automated tool has free choice as to which standard cells are placed where in order to fulfil the requirements of the functional design with a low routing overhead and to ensure the most efficient use of area taken up by cell placement.
In addition to the circuit components the standard cell defines, each standard cell may contain one or more rails to which circuit component elements of the standard cell are connected. The rails may provide fixed potentials to the circuit component elements of the standard cell. For example, each standard cell may have a high potential rail, such as a power rail (e.g., a Vdd rail), and a lower potential rail, such as a ground rail (e.g., a GND rail or a Vss rail). Upon creation of the standard cell library, components within each standard cell (e.g., circuit component elements, rails, etc.) may be fixed and difficult to modify.
Standard cell libraries with the plurality of standard cells may be created for a particular process technology. The standard cells may exhibit the physical, electrical, and performance characteristics associated with the particular process technology. As an example, for current process technologies (e.g., up to and including 20 nm technology), the standard cells may have corresponding geometries, and the metal layers used for cell rails may exhibit a corresponding resistivity. As process technologies reduce below the 20 nm technology (e.g., approaching 16 nm-14 nm domain), the techniques used to develop each of the process layers of the standard cells become significantly more complex. For example, at each process layer, the number of processes required to perform the required layout patterns increases, as techniques, such as double patterning technique (DPT), may be required to produce the layout pattern at such small process geometries. Additionally, changes in resistivity associated with the metal layers used for the standard cell rails may correspond to the smaller process geometry.
For process technologies having small process geometries (e.g., those in the 16-14 nm domain and smaller), standard cell rails may utilize a low metal layer (e.g., s metal 2 (M2) layer or metal 3 (M3) layer). The low metal layer(s) may be produced using a DPT process or may be produced using conventional lithographic techniques. The small geometry of the low metal layer coupled with its process characteristics may result in a very high resistivity for the low metal layer (e.g., M2 or M3 metal layer) and the standard cell rails that utilize it. Standard cell rails (e.g., power and ground rails), when inserted by a user of the cell library, cannot be drawn any wider because pins in some of the standard cells will no longer be accessible to the user without causing metal shorts or introducing spacing design rule check (DRC) violations.
Accordingly, standard cell rails using high resistivity metal layers which cannot be readily widened may present a user with difficulty in satisfying one or more performance requirements of an integrated circuit (“IC”) design. For example, for an IC layout design utilizing power switch standard cells, the use of standard cell rails with the low metal layer may make satisfying one or more maximum dynamic (i.e., instantaneous) voltage drop requirements (e.g., less voltage drop as possible) difficult. Placement of the power switch standard cells more closely together may lower the resistivity and corresponding voltage drop but at a cost of disturbing layout efficiency. For example, such a placement of standard cells may disturb the efficiency of area usage of the layout and may result in an undesired increase in total cell area that is used.
The use of larger standard cells with wider rails to address performance requirement issues may also present an undesired larger standard cell footprint. The larger standard cell footprint may result in increased total cell area and an undesired increase in cost. The above described problems are magnified when numerous modifications of a layout, such as a layout of a system on a chip (SoC), are to be performed to meet particular performance requirements.